The invention relates to controlling a sense amplifier, particularly to controlling sense timing of a data sense amplifier (DSA) for a memory chip.
Fast random cycle is required in a high-density memory, particularly in a dynamic random access memory (DRAM). The main bottleneck of the random cycle is the coordination between the enable timing to a memory block and the enable timing to a global DSA. Specifically, for stable DSA operation, the DSA is enabled after the arrival of data from an enabled memory block. However, from a global control that initiates data accesses and DSA enables, enabling a far memory block takes longer time than enabling a near memory block. As such, in order to ensure that the global DSA is enabled after the arrival of read data at the DSA, delay is added to the transmission of a DSA enable signal. Delaying DSA enabling time is critical for stable DSA operation, and is typically controlled by either a simple inverter delay circuit or a routing delay circulating a part of the memory chip. As such, memory cycle time is limited by DSA enabling time because enabling block and DSA need longer timing margin to accommodate the worst case scenario of enabling both the DSA and a memory block farthest from the global control.
Thus, a need exists for a DSA sensing timing control that offers the same timing characteristics whether the data is from the far block or from the near block.
The invention provides a DSA sensing timing control that offers the same timing characteristics whether the data is from the far block or from the near block.
Preferably, within a memory chip having a plurality of memory blocks, a system for controlling sensing time of a DSA comprises a global control, and a common wire path shared by all memory blocks. The global control is adapted for initiating data access to the memory blocks. The common wire path couples the global control to each memory block. The wire path is utilized by each memory block as a part of transmitting path for receiving a block enable signal sent from the global control. Moreover, each memory block is adapted to send out a DSA enable signal to the DSA in response to being selected by a block enable signal. The time from the activation of the block enable signal by the global control to the enabling of the DSA stays approximately the same irrespective of the selected memory block""s location in the memory chip.
Additionally, each memory block includes a wired-NOR circuit adapted to send out the DSA enable signal in response to the memory block receiving a block enable signal. In contrast to a simple delay circuit that only controls the DSA roughly, this wired-NOR circuit tracks internal read signal, and controls the DSA tightly. Without A driver circuit is provided for adding a delay to the propagation of the DSA enable signal from the memory block. Regardless of the enabled memory block""s location in the memory chip, the DSA is enabled after arrival of read data coming from the enabled memory block.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.